This invention relates to a logic circuit with a bipolar transistor output stage.
The characteristic feature of a CMOS logic circuit made up of P channel and N channel MOS transistors is its low current consumption. However, it involves the problem that it is difficult to increase the current drive ability for a load circuit without increasing the chip size when the circuit is integrated. For this reason, a so-called Bi/MOS logic circuit has recently been proposed. In this logic circuit, most of the circuit is made of MOS transistors, and bipolar transistors are used only for the output stage that directly drives the load circuit.
FIG. 1 shows a circuit diagram illustrating a configuration of the prior art inverter, which is a basic circuit of such a Bi/MOS logic circuit. In this circuit, P channel MOS transistor 32 and N channel MOS transistor 33 execute a logic operation in response to the signal Vin at input terminal 31. Output terminal 36 is charged and discharged with a large current by using NPN bipolar transistors 34 and 35, thereby to set output signal Vout. When input signal Vin is at an "L" or low level, P channel MOS transistor 32 is turned on, and the base current is supplied to bipolar transistor 34, from power source terminal V.sub.DD. Transistor 34 is then turned on. The output terminal is charged to an "H" or high level with a large current via transistor 34. When input signal Vin becomes high, N channel MOS transistor 33 is turned on. Then, the base current is supplied to transistor 35 via MOS transistor 33 from output terminal 36 which has been charged to a high level. With this, transistor 35 is turned on. Output terminal 36 is discharged with a large current to the low level via transistor 35.
As described above, in the FIG. 1 circuit, the output terminal is charged and discharged with a large current, thus increasing the load drive ability. In addition, as compared with the MOS transistor, the bipolar transistor allows the flow of a large current with even a small element area. This can make the chip size small when the circuit is integrated.
However, the prior art of FIG. 1 involves the problem that the current consumption is increased, since bipolar transistors 34 and 35 are provided in the output stage, and new through-current occurs between the power source terminal and ground, when these bipolar transistors are turned on and off.
FIG. 2 is an equivalent circuit diagram of the FIG. 1 circuit, in which the stray capacitances are considered. In the figure, capacitance C.sub.PD represents the stray capacitance associated with the drain of P channel MOS transistor 32. Capacitors C.sub.ND and C.sub.NS respectively represent the stray capacitances of the drain and source of N channel MOS transistor 33. Capacitors C.sub.CB and C.sub.BE respectively represent the capacitances between the base and collector and between the base and emitter of each of transistors 34 and 35. Capacitor S.sub.SUB represents the capacitance between output terminal 36 and the semiconductor substrate used when this circuit is integrated. Capacitor C.sub.L represents the load capacitance between output terminal 36 and ground. Currents I.sub.PD and I.sub.ND respectively flow through the drain of P channel MOS transistor 32 and the drain of N channel MOS transistor 33.
In this equivalent circuit, signal transistor delay time t (P.sub.DH) caused when output signal Vout rises from low to high in level is given as: ##EQU1## where V.sub.OH is the potential of the high level, and .beta. is the current-amplification factor of the bipolar transistor. The initial term of the right side of the equation represents the time required for charging transistor 34 up to the base potential of V.sub.BE. The second term represents the time required for charging transistor 34 from V.sub.BE to (V.sub.BE +V.sub.OH) to the base potential. The third term represents the time required for charging output terminal 36 to the potential of V.sub.OH.
Simplifying the equation (1) using constants, we have ##EQU2##
The signal transfer delay time t (PDL) required for output signal Vout to drop from high to low in level is given as: ##EQU3##
The initial term of the right side of the equation (3) represents the time required for charging transistor 35 up to the base potential of V.sub.BE. The second term represents the time required for charging transistor 35 from V.sub.BE to (V.sub.BE +V.sub.OH) to the base potential. The third term represents the time required for discharging output terminal 36 to the ground potential.
Simplifying the equation (3) using constants, we have ##EQU4##
As seen from equations (2) and (4), the delay time due to load capacitance C.sub.L when output terminal 36 is charged and discharged, is reduced by 1/.beta. compared to that of the prior CMOS inverter.
FIG. 3 is a graph showing the relation between the load capacitance and the delay time for both the ordinary CMOS converter and the Bi/MOS inverter. Characteristic curve A represents the characteristic of the Bi/MOS inverter. Characteristic curve B represents the characteristic of the ordinary CMOS inverter. As seen from the graph, if load capacitance C.sub.L is about 0.5 pF or more, the Bi/MOS inverter has a shorter delay time than the ordinary CMOS inverter.
The term .beta..multidot.C.sub.CB of the equation (1) and the term .beta.(C.sub.CB +C.sub.PD) of the equation (3) each represent the leak current component due to the Miller effect of the bipolar transistor. In the FIG. 1 logic circuit, the leak current component is consumed as through-current during the switching. For example, when output terminal 36 is high, if transistor 35 is turned on, and output terminal 36 is discharged to the low level, there is no discharge path for the electrons previously charged in stray capacitances C.sub.BE and C.sub.PD. For this reason, after the discharge of output terminal 36 to the low level is started, the emitter potential of transistor 36 decreases. Base current flows in transistor 34, after the voltage between the base and emitter reaches a value large enough to cause transistor 34 to turn on. Current .beta.-times as large as the base current flows in transistor 34 as collector current. Accordingly, when output signal Vout decreases from high to low, transistors 34 and 35 are both turned on, and through-current flows between power source terminal V.sub.DD and ground. Similarly when output signal Vout changes from low to high, transistors 34 and 35 are both turned on. With this, through-current flows between the power source terminal V.sub.DD and ground.
As described above, although the FIG. 1 inverter can realize the reduction of the delay time, it presents the new problem that through-current flows during the switching of transistors 34 and 35, thus increasing the current consumption. Therefore, the FIG. 1 circuit has a problem from the standpoint of practical use.
To cope with this, there have been proposed various types of improved logic circuits. FIGS. 4 through 9 show circuit diagrams of these conventional improved Bi/MOS inverters. The improvement of these inverters lies in that bypass current paths are provided for the bases of transistors 34 and 35 to prevent current leakage in bipolar transistors 34 and 35, so that the electrons charged in stray capacitances C.sub.BE and C.sub.PD can be discharged. In the FIG. 4 circuit, these bypass current paths are realized by resistors 37 and 38. In the FIG. 5 circuit, the paths are realized by two channel MOS transistors whose gates are connected commonly to power source terminal V.sub.DD. In the FIG. 6 circuit, the gate of transistor 39 in FIG. 9 is connected to input terminal 31, and the gate of transistor 40 is connected to output terminal 36, so that both transistors 39 and 40 may perform the switching only when necessary. In the FIG. 7 circuit, the gate of transistor 40 in FIG. 6 is connected to the base of transistor 34, so that transistor 40 is switched at the potential of the base node of transistor 34. In the FIG. 8 circuit, the bypass current path provided by transistor 39 is coupled with the base of transistor 35. In the FIG. 9 circuit, in addition to N channel MOS transistors 39 and 40 of the FIG. 8 circuit, N channel MOS transistor 41 is provided, whose gates, drain and source are respectively connected to input terminal 31, power source terminal V.sub.DD, and the base of transistor 35. In this circuit, since the base current for transistor 35 is also supplied from power source terminal V.sub.DD, the discharging speed of output terminal 36, when transistor 34 is turned on, can be increased.
However, in each of the FIGS. 4 to 8 circuits, the base and collector of transistor 35 are interconnected via the on-state N channel MOS transistor 33, when output signal Vout is discharged from high to low. For this reason, the base current for transistor 35 decreases when output terminal 36 is discharged and the signal Vout becomes close to the low level. This restricts the discharge of output terminal 36, to deform the waveshape of signal Vout when it falls. In the case of the FIG. 9 circuit, it is free from any waveform deformation problems, because the base current for transistor 35 can be supplied also from power source terminal V.sub.DD. However, transistor 35 is operated in the saturation region, since the current is continuously supplied via transistor 41 even after output voltage Vout is charged to the low level. Therefore, the reverse emitter current flows to output terminal 36 via a base-collector path, increasing the potential of output voltage Vout to above the ground potential. Therefore, the FIG. 9 circuit also has a problem when it is practically used.
As described above, in the prior art logic circuit including the bipolar transistors in the output stage, current consumption is increased by the provision of the bipolar transistors. The circuit with preventive measures against the increase of current consumption involves the problem that the output waveform, especially the fall of the waveform, is deformed. The circuits with the other measures have a problem in that although they do not experience the output waveform problem, the output terminal floats electrically.